1. Field
The described embodiments relate to computer systems. More specifically, the described embodiments relate to techniques for facilitating hardware transactional memory acceleration through multiple failure recovery.
2. Related Art
Modern processors that support hardware transactional memory include specialized hardware mechanisms that enable the processors to execute specified sections of program code (“protected sections”) in transactions to ensure that the protected sections are executed atomically.
When a transactional memory processor, encounters a protected section, the processor generates a checkpoint to save the pre-transactional state of the processor. The processor then begins to execute the instructions from the protected section in a transaction. While executing the transaction, the processor buffers the transactional results and uses the results for subsequent dependent transactional operations, but does not update the architectural state of the processor with the transactional results. During the transaction, the processor also monitors the execution of the instructions in the protected section and terminates the transaction if a failure condition occurs. The processor can terminate the transaction due to a number of failure conditions, such as interfering memory accesses by other threads or processors, data translation lookaside buffer (dTLB) or cache misses, or buffer overflows.
If a transaction is successful, the processor joins the transactional results with the architectural state of the processor and continues executing subsequent instructions. However, if a failure condition is encountered and the transaction is terminated, the processor performs a pipe-clear operation (to clear transactional instructions from a pipeline in the processor), discards the buffered transactional results, and resumes execution from a failure program counter (fail PC). The program code at the fail PC typically causes the processor to inspect a register that indicates why the transaction failed to enable the processor to determine how to proceed after the transaction is terminated. For example, the processor may try to perform some remedial action (e.g., send a prefetch for a cache line) before retrying the transaction. The processor then restores the checkpoint and re-executes the transaction.
Unfortunately, the processor's computational resources can be used inefficiently when the processor encounters multiple failure conditions that force the processor to re-execute the transaction multiple times.